sti5518

The STi5518 is a highly integrated single-chip decoder, designed for use in feature-rich mass-market set-top boxes. It integrates a high performance 32-bit CPU, a dedicated block for DVB/DirectTV transport demultiplexing and descrambling, modules for MPEG-2 video and audio decoding with 3D-surround and MP3 support, advanced display and graphics features, a digital video encoder, and all of the system peripherals required in a typical low-cost interactive receiver.
STI5518


Download File Sw Date
 Jak debugować.rar 03-Sep-2010
 Jak emulować.rar 03-Sep-2010
 Real-Time kernels on the ST20.rar 03-Sep-2010
 SPDIF Interface.rar 03-Sep-2010
 ST20C2&C4 Reference Manual.rar 03-Sep-2010
 STi5518 - Promo Material.rar 03-Sep-2010
 STi5518 Info.rar 03-Sep-2010
 STi5518 Small.rar 03-Sep-2010
 STi5518.rar 03-Sep-2010
 STi5518_piny.rar 03-Sep-2010
    Softcam.key   25-07-2014 25-07-2014


VIEWING PAY TV WITHOUT A VALID SUBSCRIPTION IS ILLEGAL!! ALL FILES AVAILABLE HERE ARE FOR EXPERIMENTAL AND EDUCATIONAL PURPOSE ONLY



The STi5518 is a highly integrated single-chip decoder, designed for use in feature-rich mass-market set-top boxes. It integrates a high performance 32-bit CPU, a dedicated block for DVB/DirectTV transport demultiplexing and descrambling, modules for MPEG-2 video and audio decoding with 3D-surround and MP3 support, advanced display and graphics features, a digital video encoder, and all of the system peripherals required in a typical low-cost interactive receiver.



Integrated 32-bit host CPU @ 81MHz


  • 2 Kbytes of instruction cache, 2 Kbytes of data cache, and 4Kbytes of SRAM configurable as data cache.
  • Audio decoder
  • 5.1 channel Dolby® Digital/MPEG-2 multi-channel decoding, 3 X 2-channel PCM outputs
  • IEC60958 -IEC61937 digital output
  • SRS®/TruSurround®, DTS digital out
  • DTS® digital out and MPG3 decoding
  • Alignment beep for satellite dishes
  • Video decoder
  • Supports MPEG-2 MP@ML
  • Fully programmable zoom-in and zoom-out
  • NTSC to PAL conversion
  • DVD and SVCD subpicture decoder
  • High performance on-screen display
  • 2 to 8 bits per pixel OSD options
  • Anti-flicker, anti-flutter and anti-aliasing filters
  • PAL/NTSC/SECAM encoder
  • RGB, CVBS, Y/C and YUV outputs with 10-bit DACs
  • Macrovision® 7.01/6.1 compatible (optional)
  • Shared SDRAM memory interface
  • 1 or 2x16Mbit, or 1x64Mbit 125MHz SDRAM
  • Programmable CPU memory interface for SDRAM, ROM, peripherals...
  • Front-end interface
  • DVD, VCD, SVCD and CD-DA compatible
  • Serial, parallel and ATAPI interfaces
  • Hardware sector filtering
  • Integrated CSS decryption and track buffer
  • Hardware transport-stream demultiplexor
  • Parallel/serial input
  • DES and DVB descramblers
  • 32 PID support
  • Integrated peripherals
  • 2 UARTS, 2 SmartCards, I2C controller, 3 PWM outputs, 3 capture timers
  • Modem support
  • 44 bits of programmable I/O
  • IR transmitter/receiver
  • Professional Toolset support
  • ANSI C compiler and libraries
  • 208 pin PQFP package

STi5518 : SINGLE-CHIP SET-TOP BOX DECODER


The STi5518 is a highly integrated single-chip decoder, designed for use in feature-rich mass-market set-top boxes. It integrates a high-performance 32-bit CPU, a dedicated block for DVB/DirecTV transport demultiplexing and descrambling, modules for MPEG-2 video and audio decoding with 3D-surround and MP3 support, advanced display and graphics features, a digital video encoder and all of the system peripherals required in a typical low-cost interactive receiver. To cover the needs of DVD-capable set-top boxes, STi5518 integration options include a CSS decryption block, a Dolby Digital audio decoder and Macrovision copy protection. An ATAPI interface is built-in, supporting the glueless connection of standard Hard Disk Drives. In this way, the STi5518 is ideal for set-top boxes featuring trick modes such as live TV recording, pausing and time-shifting. The STi5518 is backward compatible with the popular STi5500 set-top box decoder, allowing easy migration from the previous generation. The high level of integration in a single PQFP-208 package makes the STi5518 ideally suited for low-cost, high-volume set-top box applications.

STi5518 : WHAT IS A KERNEL?


A real-time kernel is a mechanism for controlling the execution of the tasks existing in a system. A real-time system has timing constraints governing its behaviour which mean that some actions must be carried out by particular deadlines. An example of real-time is the controlling of a fuel valve to a motor, an example of non real-time is the updating of a record in a wages data base. The important aspect of controlling the execution of tasks is that of scheduling. A realtime system must be able to perform a particular action in a particular time and thus the kernel must be able to guarantee that the task will be scheduled in a specifiable time. In other words the most important feature of a real-time kernel is that it MUST be DETERMINISTIC. The most significant aspect of the micro-kernel built into the ST20 architecture is that it is NON-DETERMINISTIC. This is so because a process is scheduled onto the back of a queue of unknown length. In many embedded systems this non-determinism does not matter, what matters is that the overall work rate keeps up with the actual data rate. In some environments, however, it matters a great deal and in these cases the ST20 micro kernel must be enhanced. A deterministic system is one in which the time taken from the occurrence of an event and the software associated with that event running on the processor has a known maximum duration. If the maximum duration is less than the required time for the application the system should be able to support the application. A standard mechanism for providing deterministic scheduling is to implement a kernel which supports multiple levels of priority in which a higher priority task will always preempt a lower priority task and the time for preemption is known. Preemption is the act of suspending the current task and starting the new task. This note is concerned with the requirements for implementing a multi-priority preemptive scheduler on the ST20.